Dual bit cells are known in the art although they are not common. Some dual bit cells have multiple threshold voltage levels, where every two threshold voltage levels together store a different bit. Others store one bit on either side of the cell. A dual bit cell of the latter kind, known as nitride, programmable read only memory (NROM) cell, is described in Applicant's copending U.S. patent application Ser. No. 08/905,286, entitled "Two Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing symmetrical Charge Trapping" which was filed Aug. 1, 1997. The disclosure of the above-identified application is incorporated herein by reference.
FIGS. 1A, 1B and 1C, to which reference is now made, schematically illustrate the dual bit NROM cell. The cell has a single channel 100 between two bit lines 102 and 104 but two separated and separately chargeable areas 106 and 108. Each area defines one bit. For the dual bit cell of FIG. 1, the separately chargeable areas 106 and 108 are found within a nitride layer 110 formed in an oxide-nitride-oxide sandwich (layers 109, 110 and 111) underneath a polysilicon layer 112.
To read the left bit, stored in area 106, right bit line 104 is the drain and left bit line 102 is the source. This is known as the "read through" direction, indicated by arrow 113. To read the right bit, stored in area 108, the cell is read in the opposite direction, indicated by arrow 114. Thus, left bit line 102 is the drain and right bit line 104 is the source.
FIG. 1B generally indicates what occurs within the cell during reading of the left bit of area 106. An analogous operation occurs when reading the right bit of area 108.
To read the left bit in area 106, the left bit line 102 receives the source voltage level V.sub.s, typically of 0V, and the right bit line 104 receives the drain voltage V.sub.d, typically of 2V. The gate receives a relatively low voltage V.sub.g, which typically is a low voltage of 3V.
The presence of the gate and drain voltages V.sub.g and V.sub.d, respectively, induce a depletion layer 54 and an inversion layer 52 in the center of channel 100. The drain voltage V.sub.d is large enough to induce a depletion region 55 near drain 104 which extends to the depletion layer 54 of channel 100. This is known as "barrier lowering" and it causes "punch-through" of electrons from the inversion layer 52 to the drain 104. The punch-through current is only minimally controlled by the presence of charge in right area 108 and thus, the left bit can be read irrespective of the presence or absence of charge in right area 108.
Since area 106 is near left bit line 102 which, for this case, acts as the source (i.e. low voltage level), the charge state of area 106 will determine whether or not the inversion layer 52 is extended to the source 102. If left area 106 has a threshold implant, then the voltage thereacross will not be sufficient to extend inversion layer 52 to the source 102 and a "0" will be read. The opposite is true if area 106 has no charge.
Like floating gate cells, the cell of FIGS. 1A and 1B is erasable and programmable. Thus, the charge stored in areas 106 and 108 can change over time in response to a user's request.
For NROM cells, each bit is programmed in the direction opposite that of its reading direction. Thus, to program left bit in area 106, left bit line 102 receives the high programming voltage (i.e. is the drain) and right bit line 104 is grounded (i.e. is the source). This is shown in FIG. 1C. The opposite is true for programming area 108.
The high programming voltage pulls electrons from the source 104. As the electrons speed up toward the drain 102, they eventually achieve enough energy to "jump" into the nitride layer 110. This is known as "hot electron injection" and it only occurs in the area close to the drain 102. When the drain voltage is no longer present, the oxide layer 109 prevents the electrons from moving back into the channel 100.
The bits are erased in the same directions that they are programmed. However, for erasure, a negative erasure voltage is provided to the gate 112 and a positive voltage is provided to the bit line which is to be the drain. Thus, to erase the charge in left area 106, the erase voltage is provided to left bit line 102. The highly negative erase voltage creates an electric field in the area near the left bit line 102 which pulls the electrons stored in the area close to the drain. However, the electric field is strong only close to the drain and thus, the charge in right area 108 is not depleted.
Typically, programming and erasure are performed with pulses of voltage on the drain and on the gate. After each pulse, a verify operation occurs in which the threshold voltage level of the cell (i.e. the level at which the cell passes current) is measured. During programming, the threshold voltage level Vtp is steadily increased so that the cell will not pass any significant current during a read operation. During erasure, the opposite is true; the threshold voltage level Vte is decreased until a significant current is present in the cell during reading.
Unfortunately, multiple erase and programming cycles change the number of pulses needed to achieve the desired threshold voltage levels. For the pulses, either the voltage level can remain constant and the number of pulses can be increased or the voltage level can be increased until the desired threshold voltage level is achieved.
The cell will no longer function once the gate voltage required for erasure is too negative and/or the number of programming pulses is reduced to one.
FIGS. 2A, 2B and 2C present experimental results of multiple programming and erase cycles, on log-linear charts. In this experiment, the gate voltage level for erasure was increased, as necessary, and the cell ceased to function after 20,000 cycles.
FIG. 2A graphs the programming and erase threshold voltage levels for both bits. Curves 60 and 62 illustrate the programming threshold voltage levels for the left and right bits, respectively, where the threshold voltage level for the right bit is measured in the forward (and not the reverse) direction. Curves 64 and 66 illustrate the erase threshold voltage levels for the left and right bits, respectively. It is noted that all curves remain relatively constant until about 2000 cycles at which point the threshold voltage levels increase. It is also noted that the programming threshold voltage level for the left bit, read in the reverse direction, is significantly higher than that for the right bit. However, the erase threshold voltage levels of each bit are smaller than their programming threshold voltage levels.
FIG. 2B illustrates the read current Ir after programming (curve 70) and after erasure (curve 72). The both currents decrease strongly after about 4000 cycles.
FIG. 2C illustrates the number of programming pulses (curve 74) and the gate voltage during erasure (curve 76). The number of programming pulses drops to one and the gate voltage drops from -6V to -9V after about 3000 cycles.